Features of the DSP-based CCD controller
  • Motorola DSP56303 based controller
  • suitable for frame transfer CCD with two output amplifiers
  • CCD clocking sequences derived from DSP code fragments
  • parallel, serial and frame transfer clocks provided
  • software programmable clock voltages and timing
  • software selectable binning and subrasters
  • software selectable signal processing gain and offsets
  • time resolution of clocks 25 ns at 80 MHz
  • two signal processing channels with 14-bit 1.25 µs A/D converter per channel
  • conversion rates of 500 kpix/sec/channel (2 µs per pixel)
  • data transfer by serial interface [10 Mbps] to PCI interface
  • integrated power supply (48 V DC input)
  • four-layer double-sided surface mount circuit boards
  • software selectable TE cooler current
  • temperature monitoring
  • source code and hardware schematics are available

Greg Burley (burley@obs.carnegiescience.edu)
Ian Thompson (ian@obs.carnegiescience.edu)