The operation of the CCD controller is set up by the host computer, which downloads the program code and sequence fragments into the DSP. Additional data loaded into the DSP specify the size of the array, the parallel and serial binning and the sequence of operations. For each operation, the DSP accesses the sequence fragment and steps through it using the associated timing information. Elementary operations such as a single pixel read or a parallel shift are repeated to read an entire line or to perform a frame transfer. The DSP executes the specified operations on a frame by frame basis, and returns data to the host computer via a fast serial interface at up to 20 Mbps.

With the appropriate sequence fragments, the CCD can be read out through one or both output amplifiers at either end of the serial register. Selectable binning and subraster patterns are built into the program code. By specifying the hold time for each data word, the host software configures the parallel and serial clock rates, and the overall frame rate.

For the frame transfer CCD, the elementary sequencing operations are shown in the diagram. The timing is set so that the serial transfers occur between the integration periods of the dual slope integrator, since there is no on-chip summing well. The pixel charge is stored in the on-chip summing well and transfered to the output node just before the signal integration period. Normal operation of the CCD involves a readout rate of 2 µs per pixel, with dual-slope integration times of 800 ns. A single three-phase parallel transfer requires 2 µs, while a single serial transfer takes 200 ns. For a 50×50 subraster, the readout time is approximately 25 ms. The device could be read out at a rate approaching 40 frames per second.

The most critical clock sequencing is required during frame transfer. Note that this is a very repetitive operation, generated by stepping through a few sequence fragments in a DO--loop. On the CCD, the rate of parallel transfer clocking is limited by the capacitance per pixel and the number of pixels per row. Since each section of the array is 1024×1024 pixels, fast transfer with parallel clock phases of 2.5 µs is feasible (frame transfer in about 5 ms). With an integration time of 100 ms, and a frame transfer time of 5 ms, the resulting on-target duty cycle is about 95%.