The basic array system electronics (BASE) design is based on a digital signal processor (Motorola DSP56303), with multiple channels of clock drivers and signal processing. The DSP directly generates the sequences used to clock the serial and parallel charge transfers on the CCDs. All of the detectors are clocked in lock-step. Each clock driver board provides independent, software programmble parallel and serial clock voltages for two detectors. Each signal processing board has two dual-slope integrator channels, each with a 1 µs 16-bit Analogic ADC4320B analog-to-digital converter. The eight channels of digitized image data are multiplexed by the DSP, and transferred by an 80 Mbps optical link to a PCI interface in a host computer running linux. The controller provides an individual temperature monitor and programmable heater current to each detector. It can provide a signal to trigger an external shutter. The DSP software directly operates the CCD controller electronics, and allows programmable features such as image size, subrastering, exposure time, binning, clock timing, signal processing gain, and offsets.
The BASE system is an open-source design -- all of the hardware schematics, circuit board layouts, programmable logic files, DSP code, interface software routines, and test results will be available on this website.
| Block diagram Features Preamplifiers DSP Timing Signal Processing Clock drivers Power/Utility Backplanes PCI Interface Temperature control Software Timing diagrams Lab test results Tools / CAD Files / Data sheets Mechanical design Photo gallery |
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Greg Burley (burley@obs.carnegiescience.edu)
Ian Thompson (ian@obs.carnegiescience.edu)